Design and Implementation of 32 Bit Systolic Array Matrix Dadda Multiplier

Authors

  • Suparna S. Nair Student, Department Electronics and Communications Engineering, VIT-AP University, Amaravathi, India
  • C. H. Deepak Professor, Department Electronics and Communications Engineering, VIT-AP University, Amaravathi, India

Keywords:

Systolic array, 32 Bit, matrix Dadda multiplier

Abstract

The most principally used operation in mathematics is multiplication. The real world applies integer multiplication whereas binary multiplication is applied for integer multiplication. The efficient algorithm to perform a binary multiplication would be systolic algorithms. Systolic array algorithms reinstate a pipeline structure with an array of processing elements that can be implied to perform a prevailing operation. This paper is developed with the perspective of designing a 32-bit systolic matrix Dadda multiplier in Icarus v10.

Downloads

Download data is not yet available.

Downloads

Published

16-12-2021

Issue

Vol. 2 No. 12 (2021)

Section

Articles

License

Copyright (c) 2021 Suparna S. Nair, C. H. Deepak

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
S. S. Nair and C. H. Deepak, “Design and Implementation of 32 Bit Systolic Array Matrix Dadda Multiplier”, IJRAMT, vol. 2, no. 12, pp. 18–19, Dec. 2021, Accessed: Sep. 08, 2024. [Online]. Available: https://journals.ijramt.com/index.php/ijramt/article/view/1587