ULSI Interconnect Scaling: Trends, Challenges and their Solutions

Abstract

Interconnects are the performance limiters in ULSI circuits connecting number of transistors as per Moore’s law. Performance of an Integrated Circuits is largely depending on these interconnect’s structure where wires are placed closer to each other with high aspect ratios. Today, interconnects account for a substantially bigger proportion of overall latency and expense in integrated circuits than in the past. Interconnect pitch reduction increases layout density but decreases interconnect RC delay. Increasing the metal aspect ratio (thickness/width) improves RC delay, although the best results are obtained when the aspect ratio is around 2. Adding more interconnect layers enhances density and performance, but within a few generations, practical limits are reached. To meet future ULSI connectivity standards, new conductor and dielectric materials, as well as enhanced circuit design methodologies, will be required. In this paper, the trends, challenges and solutions for scaling of interconnects are discussed for achieving high performance in ultra-deep submicron USLI circuits.