S. NAIR, Suparna; DEEPAK, C. H. Design and Implementation of 32 Bit Systolic Array Matrix Dadda Multiplier. International Journal of Recent Advances in Multidisciplinary Topics, [S. l.], v. 2, n. 12, p. 18–19, 2021. Disponível em: https://journals.ijramt.com/index.php/ijramt/article/view/1587.. Acesso em: 24 nov. 2024.