[1]
S. S. Nair and C. H. Deepak, “Design and Implementation of 32 Bit Systolic Array Matrix Dadda Multiplier”, IJRAMT, vol. 2, no. 12, pp. 18–19, Dec. 2021, Accessed: Sep. 16, 2024. [Online]. Available: https://journals.ijramt.com/index.php/ijramt/article/view/1587